This application claims the priority of Korean Patent Application No. 10-2004-0102282, filed on Dec. 7, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor substrate, a semiconductor device with high carrier mobility and a method of manufacturing the same.
2. Description of the Related Art
With the development of a process of manufacturing semiconductor devices, the degree of integration of semiconductor devices is improved, so that a channel length of a metal oxide semiconductor field effect transistor (hereinafter, referred to as “MOSFET”) has recently been reduced to 50 nm or less.
In a case where a channel length is shortened extremely in this manner, i.e. as a channel length shown in device scaling becomes shorter, a phenomenon that a drain current is increased is remarkably slowed down and the drain current cannot be further increased. The increase in a drain current directly leads to the increase of an operating speed of devices. It means that the improvement of the operating speed of deices cannot be achieved as high as desired only by a method of simply reducing the channel length.
To solve such a problem, studies on MOSFET devices with high mobility have been actively conducted.
First, as for high-performance MOSFETs with high mobility, a technique for increasing carrier mobility of devices by forming a MOSFET on a strained silicon substrate has been employed.
To this end, the MOSFETs have been manufactured using a special wafer on which a silicon substrate, a SiGe buffer layer, a SiGe layer and a strained silicon layer are sequentially formed. This provides a strain effect to the silicon layer using a difference between lattice structures of germanium and silicon. In other words, this is a technique for manufacturing a device such that a top strained silicon layer becomes a channel region, using a phenomenon that mobility is enhanced due to a reduced phonon distribution in a case where electrons or holes move in a strained silicon layer.
However, in a case where the MOSFET device is manufactured through the aforementioned technique, a great quantity of silicon crystal defects exists even in the top strained silicon layer due to a crystal lattice mismatch caused by a thick SiGe layer. At this time, there is a problem in that since the quantity of the silicon crystal defects is at least over 104/cm2, yield is decreased when manufacturing high integrated circuits. Further, there is another problem in that the maximum carrier mobility of the MOSFET is difficult to exceed 60%.
Next, there is another technique for applying strains only to silicon in channel regions by means of various methods after MOSFET devices have been manufactured.
According to this technique, the MOSFET has been first manufactured. Then, strains are applied to channel regions using a method of etching only source/drain regions and then selectively growing SiGe at the etched regions to apply mechanical stresses to the channel regions, or a method of forming a silicon nitride layer on the MOSFET to apply mechanical stresses to the formed silicon nitride layer.
However, there is a disadvantage in that the device manufacturing process is complicated since different kinds of strain techniques should be applied to MOSFET and PMOSFET devices, respectively, according to the aforementioned technique. Further, there is a problem in that the maximum carrier mobility of the MOSFET is difficult to exceed 60%. Furthermore, since the degree of mobility improvement varies considerably according to channel lengths, it is very difficult to extract a transistor model parameter for integrated circuit design.
Finally, there is a further technique for manufacturing Ge MOSFETs using a germanium substrate.
In this technique, since the mobility of electrons and holes is 2 to 6 times greater in a germanium substrate than in a silicon substrate, the MOSFET has been manufactured by using the germanium substrate instead of the silicon substrate, in order to increase the carrier mobility.
However, there is a problem in that the reliability of devices is reduced because it is difficult to form reliable gate dielectric layers on the germanium substrate. Further, there is a disadvantage in that since a band gap of germanium is approximately a half less than that of silicon, a junction leakage current is increased in a case where the source/drain is formed on the germanium substrate. Furthermore, there is another problem in that a silicon wafer cannot be replaced with a germanium wafer in view of a mass-production level since the production costs of the germanium wafer is five times higher than those of the silicon wafer and the germanium element is rarer than the silicon element.